1. Technical Field
The present invention relates to an analog-to-digital converter (ADC), and particularly to a predictive successive approximation register (SAR) ADC.
2. Related Art
There are multiple types of ADC architecture, for example, a flash ADC, a pipelined ADC, and a SAR ADC. These types of architecture have their own advantages. Generally, the architecture is selected according to different application requirements. The SAR ADC has the advantages of low power consumption, small area, and low cost, in comparison with other architecture.
Conventionally, the SAR ADC adopts a binary search algorithm to obtain a digital output code matching an input signal. In the process of conversion, according to each comparison result of a comparator, a digital-to-analog conversion circuit in the SAR ADC generally must add or subtract a voltage in a binary proportion, and after the last bit cycle ends, a difference between the input signal and a reference voltage is less than one least significant bit (LSB). However, in the process, it is possible that a high voltage is added to an originally small voltage difference, and then the voltage difference must be reduced gradually, resulting in a lot of unnecessary power consumption and energy waste. Additionally, this architecture requires many clock cycles (that is, bit cycles), to generate an output, which is not beneficial to high-speed operation.
Currently, there are several known technologies for increasing the speed of the SAR ADC. In one technology, more than one bit is decoded in each cycle. In this manner, three comparators are used in each clock cycle to decode two bits at a time, so for an 8-bit SAR ADC, four clock cycles rather than eight clock cycles can be used to complete conversion. In another technology, error compensation is used to tolerate a settling error, so each comparison clock cycle can be accelerated, and comparison can be performed before the voltage of the DAC is settled completely. In yet another technology, a binary SAR ADC is used to tolerate a settling error, so as to increase the speed of the SAR ADC.